Features: • High-speed access time: 10, 12, 15, and 20 ns• CMOS low power operation - 450 mW (typical) operating - 250 W (typical) standby• TTL compatible interface levels• Single 5V ± 10% power supply• I/O compatible with 3.3V device• Fully static operation: no...
IS61C3216: Features: • High-speed access time: 10, 12, 15, and 20 ns• CMOS low power operation - 450 mW (typical) operating - 250 W (typical) standby• TTL compatible interface levels• S...
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Features: • Internal self-timed write cycle• Individual Byte Write Control and Global ...
Features: • Internal self-timed write cycle• Individual Byte Write Control and Global ...
Features: • Internal self-timed write cycle• Individual Byte Write Control and Global ...
Symbol | Parameter |
Value |
Unit |
VCC | Power Supply Voltage Relative to GND |
0.5 to +7.0 |
V |
VTERM | Terminal Voltage with Respect to GND |
0.5 to+7.0 |
V |
TSTG | Storage Temperature |
65 to +150 |
|
PT | Power Dissipation |
1.5 |
W |
IOUT | DC Output Current (LOW) |
20 |
mA |
The ICSI IS61C3216 is a high-speed, 512K static RAM organized as 32,768 words by 16 bits. It is fabricated using ICSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields fast access times with low power consumption.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.
The IS61C3216 is packaged in the JEDEC standard 44-pin 400mil SOJ and 44-pin 400mil TSOP-2.