Features: `Serial Peripheral Interface (SPI) Compatible-a Supports SPI Modes 0 (0,0) and 3 (1,1)`Low-voltage Operation-a Vcc = 1.8V to 5.5`Low power CMOS-a Active current less than 3.0 mA (2.5V)-a Standby current less than 1A (2.5V)`Block Write Protection-a Protect 1/4, 1/2, or Entire Arra` 8 byte...
IS25C01: Features: `Serial Peripheral Interface (SPI) Compatible-a Supports SPI Modes 0 (0,0) and 3 (1,1)`Low-voltage Operation-a Vcc = 1.8V to 5.5`Low power CMOS-a Active current less than 3.0 mA (2.5V)-a S...
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`Serial Peripheral Interface (SPI) Compatible
-a Supports SPI Modes 0 (0,0) and 3 (1,1)
`Low-voltage Operation
-a Vcc = 1.8V to 5.5
`Low power CMOS
-a Active current less than 3.0 mA (2.5V)
-a Standby current less than 1A (2.5V)
`Block Write Protection
-a Protect 1/4, 1/2, or Entire Arra
` 8 byte page write mode
-a Partial page writes allowe
`10 MHz Clock Rate (5V)
`Self timed write cycles
-a 5 ms max. @ 2.5V
`High-reliability
-a Endurance: 1 million cycles per byt
-a Data retention: 100 year
`8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP packagesare available
`Lead-free available
Symbol |
Parameter |
Value |
Unit |
VS |
Supply Voltage |
-0.5to + 6.5 |
v |
VP |
Voltage on Any Pin |
-0.5toVcc +0.5 |
v |
TBIAS |
Temperature Under Bias |
-55 to +125 |
|
TSTG |
Storage Temperature |
-65 to +150 |
|
IOUT |
Output Current |
5 |
mA |
The IS25C01 is an electrically erasable PROM devicethat uses the Serial Peripheral Interface (SPI) forcommunications. The IS25C01 is 1Kbit(128 x 8). The IS25C01 EEPROM is offered in a wideoperating voltage range of 1.8V to 5.5V to be compatiblewith most application voltages. ISSI designed theIS25C01 to be an efficient SPIEEPROM solution. Thedevice is packaged in 8-pin PDIP, 8-pin SOIC, and 8-pinTSSOP.
The functional features of the IS25C01 allow it to beamong the most versatile serial non-volatile memoriesavailable. Each device has a Chip-Select (CS) pin, anda 3-wire interface of Serial Data In (SI), Serial Data Out(SO),andSerialClock (SCK). While the 3-wire inter-face of the IS25C01 provides for high-speed access, aHOLD pin allows the memories to ignore the interface ina suspended state; later the HOLD pin re-activatescommunication without re-initializing the serial se-quence. A Status Register facilitates a flexible writeprotection mechanism, and a device-ready bit (RDY).