Features: • Integrated 600V half-bridge gate driver• 15.6V zener clamp on Vcc• True micropower start up• Tighter initial deadtime control• Low temperature coefficient deadtime• Shutdown feature (1/6th Vcc) on CT pin• Increased undervoltage lockout Hysteres...
IR21541: Features: • Integrated 600V half-bridge gate driver• 15.6V zener clamp on Vcc• True micropower start up• Tighter initial deadtime control• Low temperature coefficient d...
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Symbol |
Definition |
Min. |
Max. |
Units | |
VB |
High side floating supply voltage |
-0.3 |
625 |
V | |
VS |
High side floating supply offset voltage |
VB - 25 |
VB + 0.3 | ||
VHO |
High side floating output voltage |
VS - 0.3 |
VB + 0.3 | ||
VLO |
Low side output voltage |
-0.3 |
VCC + 0.3 | ||
VRT |
RT pin voltage |
-0.3 |
VCC + 0.3 | ||
VCT |
CT pin voltage |
-0.3 |
VCC + 0.3 | ||
ICC |
Supply current (note 1) |
- |
25 |
mA | |
IRT |
RT pin current |
-5 |
5 | ||
dVs/dt |
Allowable offset supply voltage transient |
-50 |
50 |
V/ns | |
PD |
Package power dissipation @ TA +25°C |
(8 lead PDIP) |
- |
1.0 |
W |
(8 lead SOIC) |
- |
0.625 | |||
RTHJA |
Thermal resistance, junction to ambient |
(8 lead PDIP) |
- |
125 |
°C/W |
(8 lead SOIC) |
- |
200 | |||
TJ |
Junction temperature |
-55 |
150 |
°C | |
TS |
Storage temperature |
-55 |
150 | ||
TL |
Lead temperature (soldering, 10 seconds) |
- |
300 |
The IR21541 is an improved version of the popular IR2152 gate driver IC, and incorporates a high voltage half-bridge gate driver with a front end oscillator simi-lar to the industry standard CMOS 555 timer. The IR21541 provides more functionality and is easier to use than previous ICs. A shutdown feature has been designed into the CT pin, so that both gate driver out-puts of the IR21541 can be disabled using a low voltage control sig-nal. In addition, the gate driver output pulse widths are the same once the rising undervoltage lockout thresh-old on VCC has been reached, resulting in a more stable profile of frequency vs time at startup. Noise im-munity has been improved significantly, both by low-ering the peak di/dt of the gate drivers, and by increasing the undervoltage lockout hysteresis to 1V.Finally, special attention has been payed to maximiz-ing the latch immunity of the device, and providing comprehensive ESD protection on all pins.