IN74LV74D

The IN74LV74D  is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to- HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

The features of the IN74LV74D are: (1)Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS; (2)Supply voltage range: 1.2 to 3.6 V; (3)Low input current: 1.0 à; 0.1 mà at ò = 25 °?; (4)High Noise Immunity Characteristic of CMOS Devices.

The absolute maximum ratings of the IN74LV74D are: (1)DC Supply Voltage (Referenced to GND): -0.5 to +5.0 V ; (2)Input diode current: ±20 V ; (3)Output diode current: ±50 mA ; (4)Output diode current: ±35 mA ; (5)VCC current: ±70 mA ; (6)GND current: ±70 mA ; (7)Power dissipation per package: Plastic DIP *4: 750mW ; (8)Storage Temperature: -65 to +150 °C ; (9)Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO; (10)Package) from Case for 4 Seconds: 260 °C.