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IN74LV74

Features: ` Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS` Supply voltage range: 1.2 to 3.6 V` Low input current: 1.0 À; 0.1 mÀ at Ò = 25 °Ñ` High Noise Immunity Characteristic of CMOS DevicesPinoutSpecifications Symbol Parameter...

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SeekIC No. : 004375260 Detail

IN74LV74: Features: ` Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS` Supply voltage range: 1.2 to 3.6 V` Low input current: 1.0 À; 0.1 mÀ at Ò = 25 °&Nt...

IN74LV74 Data Sheet

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Part Number:
IN74LV74
Supply Ability:
5000

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  • 1~5000
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  • Processing time
  • 15 Days
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Product Details

Description



Features:

`  Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS
`  Supply voltage range: 1.2 to 3.6 V
`  Low input current: 1.0 À; 0.1 mÀ at Ò = 25 °Ñ
`  High Noise Immunity Characteristic of CMOS Devices


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +5.0 V
IIK*1 Input diode current ±20 V
IOK*2 Output diode current ±50 mA
IO*3 Output diode current ±35 mA
ICC VCC current ±70 mA
IGND GND current ±70 mA
PD Power dissipation per package:
Plastic DIP *4
SO *4		 750
500		 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds		 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
  Functional operation should be restricted to the Recommended Operating Conditions.
*1 VI < -0.5 V or VI > VCC + 0.5 V.
*2 VO < -0.5 V or VO > VCC + 0.5 V.
*3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
   SO Package: - 8 mW/°C from 65° to 125°C


Description

The IN74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74.

The IN74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs.

The set and reset of the IN74LV74 are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to- HIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.




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