IN74LV573

Application• Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS• Supply voltage range: 1.0 to 5.5 V• Low input current: 1.0 ; 0.1 at = 25 • High Noise Immunity Characteristic of CMOS DevicesPinoutSpecifications Symbol Parameter Value ...

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IN74LV573 Picture
SeekIC No. : 004375250 Detail

IN74LV573: Application• Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS• Supply voltage range: 1.0 to 5.5 V• Low input current: 1.0 ; 0.1 at = 25 • Hi...

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Part Number:
IN74LV573
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/24

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Product Details

Description



Application

• Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS
• Supply voltage range: 1.0 to 5.5 V
• Low input current: 1.0 ; 0.1 at = 25
• High Noise Immunity Characteristic of CMOS Devices



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC

IIK *1
DC supply voltage

Input diode current
-0.5 to +7.0

±20
V

mA
IOK *2

IO *3
Output diode current

Output source or sink current
±50

±35
mA

mA
ICC

IGND
VCC current

GND current
±70

±50
mA

mA
PD Power dissipation per package:
Plastic DIP *4
SO *4
750
500
mW
Tstg Storage Temperature -65 to +150
TL Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm
(SO Package) from Case for 4 Seconds
260


*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
*1 VI < -0.5 V or VI > VCC + 0.5 V.
*2 VO < -0.5 V or VO > VCC + 0.5 V.
*3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/ from 70° to 125
SO Package: - 8 mW/ from 70° to 125




Description

The IN74LV573 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT573.

The IN74LV573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches.

The 'IN74LV573 consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the D n inputs enters the  atches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latches.

The IN74LV573 is functionally identical to the '563' and the '373', but the 563' has inverted outputs and the '373' has a different pin arrangement.




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