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IN74LV273

Features: · Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS· Supply voltage range: 1.2 to 5.5 V· Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ· High Noise Immunity Characteristic of CMOS DevicesPinoutSpecifications Symbol Paramete...

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SeekIC No. : 004375244 Detail

IN74LV273: Features: · Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS· Supply voltage range: 1.2 to 5.5 V· Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °&N...

IN74LV273 Data Sheet

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Part Number:
IN74LV273
Supply Ability:
5000

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  • 1~5000
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Product Details

Description



Features:

·  Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS
·  Supply voltage range: 1.2 to 5.5 V
·  Low input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ
·  High Noise Immunity Characteristic of CMOS Devices


Pinout

Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
IIK*1 DC input diode current ±20 V
IOK*2 DC output diode current ±50 mA
IO*3 DC Output source or sink current ±35 mA
ICC DC VCC current ±70 mA
IGND DC GND current ±70 mA
PD Power dissipation per package: *4
Plastic DIP
SO		 750
500		 mW
Tstg Storage Temperature -65 to +150 °C
TL Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO
Package) from Case for 4 Seconds		 260 °C
*Maximum Ratings are those values beyond which damage to the device may occur.
   Functional operation should be restricted to the Recommended Operating Conditions.
*1 VI < -0.5 V or VI > VCC + 0.5 V.
*2 VO < -0.5 V or VO > VCC + 0.5 V.
*3 -0.5 V < VO < VCC + 0.5 V.
*4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C
  SO Package: - 8 mW/°C from 70° to 125°C


Description

The IN74LV273 is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC/HCT273.

The IN74LV273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flipflop.

All outputs of the IN74LV273 will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.




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