Features: • TTL/NMOS-Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 APinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND...
IN74HCT573A: Features: • TTL/NMOS-Compatible Input Levels• Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 4.5 to 5.5 V• Low Input Current: 1.0 APinoutSpecific...
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Symbol |
Parameter |
Value |
Unit |
VCC |
DC Supply Voltage (Referenced to GND) |
-0.5 to +7.0 |
V |
VIN |
DC Input Voltage (Referenced to GND) |
-1.5 to VCC +1.5 |
V |
VOUT |
DC Output Voltage (Referenced to GND) |
-0.5 to VCC +0.5 |
V |
IIN |
DC Input Current, per Pin |
±20 |
mA |
IOUT |
DC Output Current, per Pin |
±35 |
mA |
ICC |
DC Supply Current, VCC and GND Pins |
±75 |
mA |
PD |
Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ |
750 500 |
mW |
Tstg |
Storage Temperature |
-65 to +150 |
°C |
TL |
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) |
260 |
°C |
The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched.
The Output Enable input of the IN74HCT573A does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled.