IN74HC533A

Features: `Outputs Directly Interface to CMOS, NMOS, and TTL `Operating Voltage Range: 2.0 to 6.0 V `Low Input Current: 1.0 A `High Noise Immunity Characteristic of CMOS Devices PinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7....

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SeekIC No. : 004375091 Detail

IN74HC533A: Features: `Outputs Directly Interface to CMOS, NMOS, and TTL `Operating Voltage Range: 2.0 to 6.0 V `Low Input Current: 1.0 A `High Noise Immunity Characteristic of CMOS Devices PinoutSpecifications...

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Part Number:
IN74HC533A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/15

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Product Details

Description



Features:

`Outputs Directly Interface to CMOS, NMOS, and TTL  
`Operating Voltage Range: 2.0 to 6.0 V  
`Low Input Current: 1.0 A  
`High Noise Immunity Characteristic of CMOS Devices



Pinout

  Connection Diagram


Specifications

Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V
VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5
V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5
V
IIN DC Input Current, per Pin ± 20 mA
IOUT DC Output Current, per Pin ± 35 mA
ICC DC Supply Current, V CCand GND Pins
± 75 mA
PD Power Dissipation in Still Air, Plastic DIP+ 
                                        SOIC Package+
750
500
mW
Tstg Storage Temperature -65 to +150
TL Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260



Description

The IN74HC533A is identical in pinout to  the  LS/ALS533.  The device inputs are compatible with standard CMOS tputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

These latches appear transparent to data (i.e., the outputs  change asynchronously)  when Latch Enable is high. The a appears as the outputs in inverted form. When Latch Enable goes low, data meeting the setup and hold time becomes latched.

The Output Enable input of the IN74HC533A does not affect the state of the latches, but when Output Enable is high, all device outputs re forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled.




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