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IN74HC4094A

Features: `Outputs Directly Interface to CMOS, NMOS, and TTL`Operating Voltage Range: 2.0 to 6.0 V` Low Input Current: 1.0 A `High Noise Immunity Characteristic of CMOS Devices PinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -...

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IN74HC4094A: Features: `Outputs Directly Interface to CMOS, NMOS, and TTL`Operating Voltage Range: 2.0 to 6.0 V` Low Input Current: 1.0 A `High Noise Immunity Characteristic of CMOS Devices PinoutSpecifications ...

IN74HC4094A Data Sheet

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Part Number:
IN74HC4094A
Supply Ability:
5000

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Product Details

Description



Features:

`Outputs Directly Interface to CMOS, NMOS, and TTL 
`Operating Voltage Range: 2.0 to 6.0 V  
` Low Input Current: 1.0 A  
`High Noise Immunity Characteristic of CMOS Devices


Pinout

Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
 DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
 DC Input Voltage (Referenced to GND)
-1.5to VCC +1.5
V
VOUT
 DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
 DC Input Current, per Pin
±20
mA
IOUT
 DC Output Current, per Pin
±25
mA
ICC
 DC Supply Current, VCC and GND Pins
±50
mA
PD
 Power Dissipation in Still Air, Plastic DIP+ 
                                        SOIC Package+
750
500
mW
Tstg
Storage Temperature
-65 to +150
TL
 Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
260



Description

The IN74HC4094A is identical in pinout to the LS/ALS4094. The device inputs are compatible with standard CMOS outpu ts; with pullup resistors, they are compatible with LS/ALSTTL outputs.

This IN74HC4094A consists of an 8-bit shift register and 8-bit D-type latch with three-state parallel outputs. Data is shifted seri ally through the shift register on the positive going transition of the clock input signal. The output of the last stage SQH can be used to cascade several devices.

Data on the SQHoutput is transferred to a second output (SQH') on the following negative transition of the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going tr ansition of the Strobe input signal. When the Strobe input is held high, data propagates through the latch to a 3-state output buffer.

This buffer of IN74HC4094A is enabled when Output Enable input is taken high.




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