IN74HC192A

The IN74HC192A is identical in pinout to the LS/ALS192. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

The counter of the IN74HC192A has two separate clock inputs, a Count Up Clock and Count Down Clock inputs. The direction of counting is determined by which input is clocked. The outputs change state synchronous with the LOW-to-HIGH transitions on the clock inputs. This counter may be preset by entering the desired data on the P0, P1, P2, P3 input. When the Parallel Load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used  as devide-by-n by modifying the count lenght with the preset inputs. In addition the counter can also be cleared. This is accomplished by inputting a high on the Master Reset input. All 4 internal stages are set to low independently of either clock input.Both a Terminal Count Down (TC_D) and Terminal Count Up (TC_U) Outputs are provided to enable cascading of both up and down counting functions. The TC_D output produces a negative going pulse when the counter underflows and TC_U outputs a pulse when the counter  and TC_U overflows. The counter of the IN74HC192A can be cascaded by connecting the TC_D outputs of one device to the Count Up Clock and Count Down Clock inputs, respectively, of the next device.