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IN74HC175A

Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A• High Noise Immunity Characteristic of CMOS DevicesPinoutSpecifications SYMBOL PARAMETER Value Unit VCC Supply voltage(Referenced to GN...

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SeekIC No. : 004375014 Detail

IN74HC175A: Features: • Outputs Directly Interface to CMOS, NMOS, and TTL• Operating Voltage Range: 2.0 to 6.0 V• Low Input Current: 1.0 A• High Noise Immunity Characteristic of CMOS Dev...

IN74HC175A Data Sheet

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Part Number:
IN74HC175A
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices


Pinout

Connection Diagram


Specifications

SYMBOL PARAMETER Value Unit
VCC Supply voltage(Referenced to GND) -0.5 to +7.0 V
VIN Input voltage(Referenced to GND) -1.5 to VCC +1.5 V
VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V
IIN DC Input Current, per Pin ±20 mA
IOUT DC Output Sink/Source Current, per Pin ±25 mA
ICC DC Supply Current, VCC and GND Pins ±50 mA
PD Power Dissipation in Still Air, Plastic DIP+
SOIC Package+		 750
500		 mW
TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260
Tstg Storage Temperature -65 to +150
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65 to 125
SOIC Package: : - 7 mW/ from 65to 125


Description

The IN74HC175A is identical in pinout to the LS/ALS175. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

This IN74HC175A consists of four D flip-flops with common Reset and Clock inputs, and separate D inputs. Reset (active-low) is asynchronous and occurs when a low level is applied to the Reset input. Information at a D input is transferred to the corresponding Q output on the next positive-going edge of the Clock input.




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