IN74HC123A

PinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input...

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SeekIC No. : 004374976 Detail

IN74HC123A: PinoutSpecifications Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1...

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Part Number:
IN74HC123A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Pinout

  Connection Diagram


Specifications

Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
VIN
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
VOUT
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
IIN
DC Input Current, per Pin
A, B, CLR CX, RX
±20 ±30
mA
IOUT
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air, Plastic DIP+ SOIC Package+
750 500
mW
Tstg
Storage Temperature
-65 to +150
TL
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/ from 65° to 125
SOIC Package: : - 7 mW/ from 65° to 125



Description

The IN74HC123A is identical in pinout to the LS/ALS123. The device inputs are compatible with standard CMOS  outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

There are two trigger inputs, A INPUT (negative edge) and B INPUT (positive edge). These inputs of the IN74HC123A are valid for rising/falling signals.

The device may also be triggered by using the CLR input (positive-edge) because of the Schmitt-trigger input; after triggering the output maintains the MONOSTABLE state for the time period determined by the external resistor RX and capacitor CX. Taking CLR low breaks this MONOSTABLE STATE. If the next trigger pulse occurs during the MONOSTABLE period it makes the MONOSTABLE period longer.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 3.0 to 6.0 V
• Low Input Current: 1.0 A
• High Noise Immunity Characteristic of CMOS Devices




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