IDTQS34XST257

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc Terminals.
3. All terminals except Vcc.

The IDTQS34XST257 is a high-speed CMOS quad 32:16 multiplexer/ demultiplexer with active terminators (bus-hold circuits) on the demux side. It is organized as four independent quad 2:1 mux/demux blocks. Port selection and connection, controlled by SEL signals, can be either asynchronous or synchronous. In the synchronous mode, the A or B port to Y port connection is updated on the rising edge of the input clock CLK. Once the port-to-port connection is made, data flow can be bi-directional with a typical 250ps propagation delay through the switch. Clock Enable, overriding Asynchronous Enable, and Asynchronous Select controls provide additional design flexibility.

The bus-hold circuits latch the last data driven on the demux side, providing infinite hold time and glitch-free signal transitions. Synchronous controls and bus-hold ease timing constraints in many high speed data mux/  demux applications, such as bank interleaving. The IDTQS34XST257 is available in the space-saving, 80-pin dual-in-line MillipaQ package.

The IDTQS34XST257 is characterized for operation at -40°C to +85°C.