IDTCV110L

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

IDTCV110L is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip of IDTCV110L has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. IDTCV110L also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has IDTCV110L own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups.