IDTCV110J

IDTCV110J is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor.  This chip has three PLLs inside for CPU/SRC/PCI, SATA, and 48MHz/DOT96 IO clocks.  One dedicated PLL for Serial ATA clock provides high accuracy frequency.  IDTCV110J also implements Band-gap referenced I_REF to reduce the impact of V_DD variation on differential outputs, which can provide more robust system performance.

Static PLL frequency divide error of IDTCV110J can be as low as 36 ppm, worse case 114ppm, providing high accuracy output clock.  Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting  other clock groups.