Features: • 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
• Operating frequency: 125MHz to 410MHz
• Stabilization time: <6us
• Very low skew: 40ps
• Very low jitter: 40ps
• 1.8V AVDD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packagesApplication• Meets or exceeds JEDEC standard CUA877 for registered DDR2 clock driver
• Along with SSTUA32864/66, DDR2 register, provides complete solution for DDR2 DIMMsPinout
Specifications
| Symbol |
Rating |
Max |
Unit |
| VDDQ, AVDD |
Supply Voltage Range |
0.5 to +2.5 |
V |
| VI(3) |
Input Voltage Range |
0.5 to VDDQ + 0.5 |
V |
| VO(3 |
Voltage range applied to any
output in the high or low state |
0.5 to VDDQ + 0.5 |
V |
| IIK(VI <0) |
Input clamp curr |
±50 |
mA |
IOK
(VO <0 or
VO > VDDQ |
Output Clamp Current |
±50 |
mA |
IO
(VO =0 to VDDQ) |
Output Clamp Current |
±50 |
mA |
| VDDQ or GND |
Output Clamp Current |
±100 |
mA |
| TSTG |
Output Clamp Current |
65 to +150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max.
DescriptionThe CSPUA877A is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) IDTCSPUA877A for synchronization of the outputs to the input reference of IDTCSPUA877A is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, IDTCSPUA877A will enter a low power-down mode.
In this mode, the receivers IDTCSPUA877A are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a clock driver current consumption of less than 500A.
The CSPUA877A requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPUA877 , designed for use in both module assemblies of IDTCSPUA877A and system motherboard based solutions, provides an optimum high-performance clock source.
The CSPUA877A is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.
IDTCSPUA877A Data Sheet
