Features: • 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
• Operating frequency: 125MHz to 400MHz
• Very low skew: 40ps
• Very low jitter: 40ps
• 1.8V AVDD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clockApplication• Meets or exceeds JEDEC standard 82.8 for registered DDR2 clock driver
• Along with SSTU32864/A, DDR2 register, provides complete solution for DDR2 DIMMsPinout
Specifications
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any
output in the high or low state |
VO(2) |
0.5 to VDD + 0.5
|
V |
|
Input clamp current
|
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect
to GND (inputs VIH 2.5, VIL 2.5) |
IOK
(VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
100 |
mA |
|
Storage Temperature Range |
TSTG |
65 to +150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max.
Description The CSPU877 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference of IDTCSPU877 is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, IDTCSPU877 will enter a low power-down mode. In this mode of IDTCSPU877, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500µA.
The CSPU877 requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range.
The CSPU877, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877 is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.
IDTCSPU877 Data Sheet
