IDTCSPT857D

The CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs of IDTCSPT857D to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the input frequency falls below approximately 20MHz, IDTCSPT857D will enter power down mode. In this mode of IDTCSPT857D, the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption of less than 200µA.

The CSPT857D requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPT857D, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source.

The CSPT857D is available in Commercial Temperature Range (0°C to +70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details.