Features: • Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications
• Operating frequency: 60MHz to 200MHz
• Standard speed: PC1600 (DDR200), PC2100 (DDR266)
• A speed: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333)
• 1 to 10 differential clock distribution
• Very low skew (<100ps)
• Very low jitter (<75ps)
• 2.5V AVDD and 2.5V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 48-pin TSSOP and 56-pin VFBGA packagesPinout
Specifications
|
Rating |
Symbol |
Max |
unit |
|
Supply Voltage Range |
V CC1, VCC2 |
0.5 to +4.6
|
V |
|
Input Voltage Range |
VI (2)
|
0.5 to +5.5 |
V |
|
Voltage range applied to any
output in the high or low state |
VO(2) |
0.5 to VDDQ + 0.5
|
V |
|
Input clamp current
|
IIK (VI < 0)
|
50 |
mA |
|
Terminal Voltage with Respect
to GND (inputs VIH 2.5, VIL 2.5) |
IOK
(VO < 0 or VO > VDD) |
-50
|
mA |
|
Continuous Output Current |
IRES |
±100 |
mA |
|
Continuous Current |
VDD or GND |
65 to +150 |
mA |
|
Junction Temperature |
TSTG |
+150 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
DescriptionThe CSPT857 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK,CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT).
External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin of IDTCSPT857A is available for low power disable. When the output frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL IDTCSPT857A is turned off, and the output clock drivers are tristated, resulting in a current consumption device of less than 200µA.
The CSPT857 requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range.
The CSPT857, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPT857 is only available in Industrial Temperature Range (-40°C to +85°C), and CSPT857A is only available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details.
IDTCSPT857A Data Sheet
