IDTCSPT855

The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs FBOUT, FBOUT). When PWRDWN IDTCSPT855 is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs of IDTCSPT855 are disabled to a highimpedance state (3-state), and the PLL is shut down (low-power mode).

IDTCSPT855 also enters this low-power mode when the input frequency falls below suggested detection frequency that is below 20MHz (typical 10MHz). An input frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs. When AVDD IDTCSPT855 is tied to GND, the PLL is turned off and bypassed for test purposes.

The CSPT855 is also able to track spread spectrum clocking reducted EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up.