IDTCSPF2510C

The IDTCSPF2510C is a high performance, low-skew, low-phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, infrequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.

The CSPF2510C operates at 3.3V and provides integrated series-damping resistors that make IDTCSPF2510C ideal for driving point-to-point loads, single or dual. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs of IDTCSPF2510C can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSPF2510C does not require external RC networks.

The loop filter IDTCSPF2510C for the PLL is included on-chip, minimizing component count, board space, and cost. Because IDTCSPF2510C is based on PLL circuitry, the CSPF2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL IDTCSPF2510C reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground.

The CSPF2510C is characterized for operation from 0°C to +85°C. This device is also available (on special order) in Industrial (-40°C to +85°C)