IDTCSP2510D

The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. IDTCSP2510D uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.

The CSP2510D operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles of IDTCSP2510D are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510D does not require external RC networks. The loop filter IDTCSP2510D for the PLL is included on-chip, minimizing component count, board space, and cost.

Because IDTCSP2510D  is based on PLL circuitry, the CSP2510D requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510D is specified for operation from 0°C to +85°C. IDTCSP2510D is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details.