IDTCSP2510CPGG

Series: -
Number of Circuits: 1
Differential - Input:Output: No/No
Mounting Type: Surface Mount
Divider/Multiplier: No/No
Packaging: Tube
Input: Clock
Output: Clock
PLL: Yes with Bypass
Voltage - Supply: 3 V ~ 3.6 V
Operating Temperature: 0°C ~ 85°C
Frequency - Max: 140MHz
Package / Case: 24-TSSOP (0.173", 4.40mm Width)
Supplier Device Package: 24-TSSOP
Ratio - Input:Output: 1:10
Manufacturer: IDT, Integrated Device Technology Inc
Type: PLL Driver, Zero Delay Buffer


Features:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications
• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V VDD
• tpd Phase Error at 133MHz: < ±150ps
• Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz
• Spread Spectrum Compatible
• Operating frequency 25MHz to 140MHz
• Available in 24-Pin TSSOP package


Application

• SDRAM Modules
• PC Motherboards
• Workstations


Pinout




Specifications

Symbol	Rating	Max	Unit
VDD VI(1) VO(1,2) IIK (VI <0) IOK (VO <0 or VO > VDD) IO (VO = 0 to VDD) VDD or GND TSTG TJ	Supply Voltage Range Input Voltage Range Voltage range applied to any output in the high or low state Input clamp current Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) Continuous Output Current Continuous Current Storage Temperature Range Junction Temperature	0.5 to +4.6 0.5 to +6.5 0.5 to VDD + 0.5 50 ±50 ±50 ±100 65 to +150 +150	V V V mA mA mA mA °C °C

Description

The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. IDTCSP2510CPGG is specifically designed for use with synchronous DRAMs. The CSP2510C operates at 3.3V.

One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles of IDTCSP2510CPGG are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the CSP2510C does not require external RC networks. The loop filter IDTCSP2510CPGG for the PLL is included on-chip, minimizing component count, board space, and cost.

Because IDTCSP2510CPGG is based on PLL circuitry, the CSP2510C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL IDTCSP2510CPGG can be bypassed for the test purposes by strapping AVDD to ground.

The CSP2510C is specified for operation from 0°C to +85°C. This device is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details.

Parameters:

Technical/Catalog Information	IDTCSP2510CPGG
Vendor	IDT, Integrated Device Technology Inc
Category	Integrated Circuits (ICs)
Type	PLL Clock Driver, Zero Delay Buffer
Voltage - Supply	3 V ~ 3.6 V
Number of Outputs	10
Input	Clock
Output	Clock
Frequency-Max	140MHz
Package / Case	24-TSSOP
Packaging	Tube
Operating Temperature	0°C ~ 70°C
Lead Free Status	Lead Free
RoHS Status	RoHS Compliant
Other Names	IDTCSP2510CPGG IDTCSP2510CPGG 800 1706 5 ND 80017065ND 800-1706-5