Features: • Advanced Memory Buffer for Fully buffered DIMMs• 3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)• Support for up to eight DIMMs per channel• Repeater Mode for extending FB-DIMM links• Northbound and Southbound single lane fail over and channel error...
IDTAMB0480: Features: • Advanced Memory Buffer for Fully buffered DIMMs• 3.2 and 4 Gbit/s serial speeds (DDR2-533 and 667 DRAM)• Support for up to eight DIMMs per channel• Repeater Mode ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Symbol |
Description |
Min |
Max |
Unit |
VDD | Supply voltage DRAM Interface |
-0.5 |
+2.3 |
V |
VIN(DDR2). VOUT(DDR2) |
Voltage on any DDR2 interface pin relative to Vss(2) |
0.5 |
+2.3 |
V |
IINK | Input Clamp Current (VIN < 0 or VIN > VDD) |
+30 |
mA | |
IOUTK | Output Clamp Current(VOUT < 0 or VOUT > VDD) |
+30 |
mA | |
IOUT | Continous Output Current(VOUT = 0 to VDD) |
+30 |
mA | |
N/A | Continuous current through each VDD or GND |
+100 |
mA | |
VCC | Supply voltage for Core and High Speed Interface |
-0.3 |
+1.75 |
V |
TJ | Junction Temperature |
+125 |
°C | |
TSTG | Storage Temperature Range |
-55 |
+100 |
°C |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the evice. This is a stress rating only and functional operation of the device at these or any other conditions above those ndicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.3V maximum.
The fully buffered dual in-line memory module (FB-DIMM)IDTAMB0480 is the next generation memory architecture to meet the growing memory requirement of servers and workstations. The IDT IDTAMB0480 Advanced Memory Buffer (AMB) chip is the essential building block located on each FB-DIMM. The IDTAMB0480 receives commands and data from the host controller to control and write/read data to/from the DRAMs on the DIMM. Commands and write data are sent southbound from the host controller to AMBs in a daisy chain fashion and interpreted by the target AMB. Status and read data are sent northbound from AMBs to the host controller also in a daisy chain fashion, passing through non-target AMBs. IDTAMB0480 unique channel structure alleviates buffer loading issues common in registered DIMM technology, enabling designers to use a large number of DIMMs within a single system.
IDTAMB0480 complies with the latest JEDEC defined FB-DIMM Architecture and Protocol Specification and supports DDR2-533 and DDR2-667 DRAM.It also enables serial data transfer at 3.2 and 4.0Gbps. The IDTAMB0480 supports servers, workstations, storage devices and communication applications that support the next generation FB-DIMM architecture.