IDT82V3280

HIGHLIGHTS
• The first single PLL chip:
• Features 0.5 mHz to 560 Hz bandwidth
• Exceeds GR-253-CORE (OC-12) and ITU-T G.813 (STM-16/ Option I) jitter generation requirements
• Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
• Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments MAIN FEATURES
• Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 2, 3E, 3, SMC, 4E and 4 clocks
• Employs DPLL and APLL to feature excellent jitter performance and minimize the number of the external components
• Integrates T0 DPLL and T4 DPLL; T4 DPLL locks independently or locks to T0 DPLL
• Supports Forced or Automatic operating mode switch controlled by an internal state machine; the primary operating modes are Free- Run, Locked and Holdover
• Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps)
• Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
• Supports PBO to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
• Supports phase absorption when phase-time changes on T0 selected input clock are greater than a programmable limit over an interval of less than 0.1 seconds
• Supports programmable input-to-output phase offset adjustment
• Limits the phase and frequency offset of the outputs
• Supports manual and automatic selected input clock switch
• Supports automatic hitless selected input clock switch on clock failure
• Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
• Provides a 2 kHz, 4 kHz or 8 kHz frame sync input signal, and a 2 kHz and an 8 kHz frame sync output signals
• Provides 14 input clocks whose frequency cover from 2 kHz to 622.08 MHz
• Provides 9 output clocks whose frequency cover from 1 Hz to 622.08 MHz
• Provides output clocks for BITS, GPS, 3G, GSM, etc.
• Supports AMI, PECL/LVDS and CMOS input/output technologies
• Supports master clock calibration
• Supports Master/Slave application (two chips used together) to enable system protection against single chip failure
• Meets Telcordia GR-1244-CORE, GR-253-CORE, GR-1377- CORE, ITU-T G.812, ITU-T G.813 and ITU-T G.783 criteria OTHER FEATURES
• Multiple microprocessor interface modes: EPROM, Multiplexed, Intel, Motorola and Serial
• IEEE 1149.1 JTAG Boundary Scan
• Single 3.3 V operation with 5 V tolerant CMOS I/Os
• 100-pin TQFP package, Green package options available

The IDT82V3280 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 2, 3E, 3, SMC, 4E and 4 clocks in SONET / SDH equipments, DWDM and Wireless base station, such as GSM, 3G, DSL concentrator, Router and Access Network applications.

IDT82V3280 supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing.

Based on ITU-T G.783 and Telcordia GR-253-CORE, IDT82V3280 consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path.

An input clock of IDT82V3280 is automatically or manually selected for T0 and T4 each for DPLL locking. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode,the DPLL refers to the master clock. In Locked mode, the DPLL locks tothe selected input clock. In Holdover mode, the DPLL resorts to the frequency data of IDT82V3280 acquired in Locked mode. Whatever the operating mode is,the DPLL gives a stable performance without being affected by operating conditions or silicon process variations.

If the DPLL outputs are processed by T0/T4 APLL, the outputs of IDT82V3280 will be in a better jitter/wander performance.

IDT82V3280 provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements.

A high stable input is required for the master clock in different applications.

The master clock is used as a reference clock for all the internal circuits in the device. IDT82V3280 can be calibrated within ±741 ppm.

All the read/write registers are accessed through a microprocessorinterface. IDT82V3280 supports five microprocessor interface modes:EPROM, Multiplexed, Intel, Motorola and Serial.

In general, IDT82V3280 can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure. See Chapter 4 Typical Application for details.