IDT82V2108

• Octal Framer supporting T1, E1 and J1 Formats
• Provides programmable system interface to support Mitel® STbus, AT&T®CHI and MVIP bus, supporting data rates of 1.544 / 2.048 / 8.192Mb/s; up to four links can be byte interleaved on one system bus without external logic
• Provides up to three internal floating HDLC controllers for each framer to support ISDN PRI and V5.X interface. Each HDLC contains 128-byte deep FIFOs in both the receive and transmit directions
• Provides jitter attenuation performance exceeding the requirements set by the associated standards for both Rx and Tx path
• Provides payload, line and digital loop-backs
• Provides a floating Pseudo Random Bit Sequence / repetitive pattern generator/detector, which can be assigned to any one of eight framers, the pattern may be inserted / detected in an unframed or Nx64K or Nx56K (T1 only) basis
• Provides signaling insertion / extraction for CCS / CAS and RBS signaling system
• Provides programmable codes insertion, data / sign inversion and digital milliwatt code insertion on a per channel / timeslot basis
• Supports automatic / manual alarming transmit and integration
• Provides performance monitor to counter CRC error, framing bit error, far end block CRC error (E1), out of frame event (T1/J1) and change of frame alignment event (T1/J1)
• Provides programmable In-band Loop-back Code transmitter/receiver, Bit Oriented Message generator / detector
• Supports polled or interrupt driven processing for all events
• Supports multiplexed or non-multiplexed address/data bus MPU interface for configuration, control and status monitoring
• JTAG boundary scan meets IEEE 1149.1
• Low power 3.3V CMOS technology with 5V tolerant inputs
• Operating industrial temperature range: -40°C to +85°C
• Package available: 128 pin PQFP 144 pin PBGA

The IDT82V2108 is a flexible feature-rich octal T1/E1/J1 Framer. Controlled by the software, the IDT82V2108 can be globally configured as an Octal E1 or T1/J1 Framer. When E1 or T1/J1 has been set globally, the operation mode of each of the eight framers can be configured independently. The configuration is performed through a parallel Multiplexed/Non-Multiplexed microprocessor interface.

The IDT82V2108 realizes frame synchronization, frame generating, signaling extraction and insertion, alarm and test signals generation and detection in a single chip. It also integrates up to three HDLC receivers and HDLC transmitters for each of the eight framers.

In E1 Mode, the receive path of each framer can be configured to frame to Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be bypassed (unframed mode). IDT82V2108 detects and indicates the event of out of Basic Frame Sync, out of CRC Multi- Frame, out of Signaling Multi-Frame, the Remote Alarm Indication signal and the Remote Signaling Multi-Frame Alarm Indication signal. IDT82V2108 also monitors the Red and AIS alarms. Basic Frame Alignment Signal errors, Far End Block Errors (FEBE) and CRC errors are counted. Up to three HDLC links are provided to extract the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. An Elastic Store Buffer that optionally supports slip buffering and adaptation to backplane timing is provided. In E1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, trunk conditioning, data inversion and pattern generation or detection are also supported on a per-timeslot basis.

In E1 mode, the transmit path of each framer of IDT82V2108 can be configured to generate Basic Frame, CRC Multi-Frame and Signaling Multi-Frame. The framing can also be disabled (unframed mode). IDT82V2108 can also transmit Remote Alarm Indication signal, the Remote Signaling Multi-Frame Alarm Indication signal, AIS signal and FEBE. Up to three HDLC links are provided to insert the HDLC message on TS16, the Sa National bits and/or any arbitrary timeslot. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-timeslot basis.

In E1 mode of IDT82V2108, any four of the eight framers can be multiplexed or demultiplexed to or from one of the two 8.192M bit/s buses.

In T1/J1 mode, the receive path of each framer can be configured to frame to Super Frame (SF) or Extended Super Frame (ESF) formats. The framing can also be bypassed (unframed mode). IDT82V2108 detects and indicates the out of SF/ESF sync event, the Yellow, Red and AIS alarms. IDT82V2108 also detects the presence of inband loopback codes, bit oriented message. Frame Alignment Signal errors, CRC-6 errors, out of SF/ESF events and Frame Alignment position changes are counted. Up to two HDLC links are provides to extract the HDLC message on the Fbit or any arbitrary channels in ESF mode. An Elastic Store Buffer that optionally supports controlled slip and adaptation to backplane timing is provided. In T1/J1 receive path, signaling debounce, signaling freezing, idle code substitution, digital milliwatt code insertion, idle code insertion, data inversion and pattern generation or detection are also supported on a per-channel basis.

In T1/J1 mode, the transmit path of each framer can be configured to generates SF or ESF. The framing of IDT82V2108 can also be disabled (unframed mode). IDT82V2108 can also transmit Yellow signal and AIS signal. Inband loopback codes and bit oriented message can also be transmitted. Up to two HDLC links are provided to insert the HDLC message on the F-bit or any arbitrary channels in ESF mode. The signaling insertion, idle code substitution, data insertion, data inversion and test pattern generation or detection are also supported on a per-channel basis.

In T1/J1 mode, the data stream of 1.544M bit/s can be converted to/ from the data stream of 2.048M bit/s on the system side of IDT82V2108 by software configuration. In addition, any four of the eight framers can be multiplexed or de multiplexed to or from one of the two 8.192M bit/s buses.