IDT82P2828

Features:

Integrates 28+1 channels T1/E1/J1 short haul line interface units for 100 T1, 120 E1, 110 J1 twisted pair cable and 75 E1 coaxial cable applications
Per-channel configurable Line Interface options
  • Supports various line interface options
    Differential and Single Ended line interfaces
    true Single Ended termination on primary and secondary side of transformer for E1 75 coaxial cable applications
    transformer-less for Differential interfaces
  • Fully integrated and software selectable receive and transmit termination
    Option 1: Fully Internal Impedance Matching with integrated receive termination resistor
    Option 2: Partially Internal Impedance Matching with common external resistor for improved device power dissipation
    Option 3: External impedance Matching termination
  • Supports global configuration and per-channel configuration to T1, E1 or J1 mode
Per-channel programmable features
  • Provides T1/E1/J1 short haul waveform templates and userprogrammable arbitrary waveform templates
  • Provides two JAs (Jitter Attenuator) for each channel of receiver and transmitter
  • Supports AMI/B8ZS (for T1/J1) and AMI/HDB3 (for E1) encoding and decoding
Per-channel System Interface options
  • Supports Single Rail, Dual Rail with clock or without clock and sliced system interface
  • Integrated Clock Recovery for the transmit interface to recover transmit clock from system transmit data
Per-channel system and diagnostic functions
  • Provides transmit driver over-current detection and protection with optional automatic high impedance of transmit interface
  • Detects and generates PRBS (Pseudo Random Bit Sequence), ARB (Arbitrary Pattern) and IB (Inband Loopback) in either receive or transmit direction
  • Provides defect and alarm detection in both receive and transmit directions.
    Defects include BPV (Bipolar Violation) /CV (Code Violation) and EXZ (Excessive Zeroes)
    Alarms include LLOS (Line LOS), SLOS (System LOS), TLOS (Transmit LOS) and AIS (Alarm Indication Signal)
  • Programmable LLOS detection /clear levels. Compliant with ITU and ANSI specifications
  • Various pattern, defect and alarm reporting options
    Serial hardware LLOS reporting (LLOS, LLOS0) for all 29 channels
    Configurable per-channel hardware reporting with RMF/TMF (Receive /Transmit Multiplex Function)
    Register access to individual registers or 16-bit error counters
  • Supports Analog Loopback, Digital Loopback and Remote Loopback
  • Supports T1.102 line monitor
Channel 0 monitoring options
  • Channel 0 can be configured as monitoring channel or regular channel to increase capacity
  • Supports all internal G.772 Monitoring for Non-Intrusive Monitoring of any of the 28 channels of receiver or transmitter
  • Jitter Measurement per ITU O.171
Hitless Protection Switching (HPS) without external Relays
  • Supports 1+1 and 1:1 hitless protection switching
  • Asynchronous hardware control (OE, RIM) for fast global high impedance of receiver and transmitter (hot switching between working and backup board)
  • High impedance transmitter and receiver while powered down
  • Per-channel register control for high impedance, independent for receiver and transmitter
Clock Inputs and Outputs
  • Flexible master clock (N x 1.544 MHz or N x 2.048 MHz) (1 N 8, N is an integer number)
  • Two selectable reference clock outputs
    from the recovered clock of any of the 29 channels
    from external clock input
    from device master clock
  • Integrated clock synthesizer can multiply or divide the reference clock to a wide range of frequencies: 8 KHz, 64 KHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 19.44 MHz and 32.768 MHz
  • Cascading is provided to select a single reference clock from multiple devices without the need for any external logic
Microprocessor Interface
  • Supports Serial microprocessor interface and Parallel Intel / Motorola Non-Multiplexed /Multiplexed microprocessor interface
Other Key Features
  • IEEE1149.1 JTAG boundary scan
  • Two general purpose I/O pins
  • 3.3 V I/O with 5 V tolerant inputs
  • 3.3 V and 1.8 V power supply
  • Package: 640-pin TEPBGA (31 mm X 31 mm)
Applicable Standards
  • AT&T Pub 62411 Accunet T1.5 Service
  • ANSI T1.102, T1.403 and T1.231
  • Bellcore TR-TSY-000009, GR-253-CORE and GR-499-CORE
  • ETSI CTR12/13
  • ETS 300166 and ETS 300 233
  • G.703, G.735, G.736, G.742, G.772, G.775, G.783 and G.823
  • O.161
  • ITU I.431 and ITU O.171


Application

SDH/SONET multiplexers
Central office or PBX (Private Branch Exchange)
Digital access cross connects
Remote wireless modules
Microwave transmission systems


Specifications

Symbol	Parameter	Min	Max	Unit
VDDD	Digital Core Power Supply	-0.5	2.2	V
VDDA	Analog Core Power Supply	-0.5	4.6	V
VDDIO	I/O Power Supply	-0.5	4.6	V
VDDT0~28	Power Supply for Transmitter Driver	-0.5	4.6	V
VDDR0~28	Power Supply for Receiver	-0.5	4.6	V
Vin	Input Voltage, Any Digital Pin	GND - 0.5	6	V
	Input Voltage, Any RTIP and RRING pin 1	GND - 0.5	VDDR + 0.5	V
	ESD Voltage, Any Pin 2	2000		V
Iin	Transient Latch-up Current, Any Pin		100	mA
	Input Current, Any Digital Pin 3	-10	10	mA
	DC Input Current, Any Analog Pin 3		±100	mA
Pd	Maximum Power Dissipation in Package		2.4 4	W
Tj	Junction Temperature		125
Ts	Storage Temperature	-65	+150
Note: 1. Reference to ground. 2. Human body model. 3. Constant input current. 4. If device power consumption exceeds this value, a heatsink must be used. Refer to Chapter 7 Thermal Management. Caution: Exceeding the above values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

Description

The IDT82P2828 is a 28+1 channels high-density T1/E1/J1 short haul Line Interface Unit. Each channel of the IDT82P2828 can be independently configured. The configuration is performed through a Serial or Parallel Intel/Motorola Non-Multiplexed /Multiplexed microprocessor interface.

In the receive path, through a Single Ended or Differential line interface, the received signal is processed by an adaptive Equalizer and then sent to a Slicer. Clock of IDT82P2828 and data are recovered from the digital pulses output from the Slicer. After passing through an enabled or disabled Receive Jitter Attenuator, the recovered data of IDT82P2828 is decoded using B8ZS/ AMI/HDB3 line code rule in Single Rail NRZ Format mode and output to the system, or output to the system without decoding in Dual Rail NRZ Format mode and Dual Rail RZ Format mode.

In the transmit path, the data to be transmitted is input on TDn in Single Rail NRZ Format mode or TDPn/TDNn in Dual Rail NRZ Format mode and Dual Rail RZ Format mode, and is sampled by a transmit reference clock. The clock can be supplied externally from TCLKn or recovered from the input transmit data by an internal Clock Recovery. A selectable JA in Tx path is used to de-jitter gapped clocks. To meet T1/ E1/J1 waveform standards, five preset T1 templates and two E1 templates, as well as an arbitrary waveform generator are provided. The data of IDT82P2828 through the Waveform Shaper, the Line Driver and the Tx Transmitter is output on TTIPn and TRINGn.

Alarms (including LOS, AIS) and defects (including BPV, EXZ) IDT82P2828 are detected in both receive line side and transmit system side. AIS alarm, PRBS, ARB and IB patterns can be generated /detected in receive / transmit direction for testing purpose. Analog Loopback, Digital Loopback and Remote Loopback are all integrated for diagnostics.

Channel 0 is a special channel. Besides normal operation as the other 28 channels, channel 0 also supports G.772 Monitoring and Jitter Measurement per ITU O.171.

A line monitor function per T1.102 is available to provide a Non-Intrusive Monitoring of channels of other devices.

JTAG per IEEE 1149.1 is also supported by the IDT82P2828.