IDT74LVCH32373A

Features: • Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• CMOS power levels (0.4 W typ. static)• All in...

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IDT74LVCH32373A Picture
SeekIC No. : 004373224 Detail

IDT74LVCH32373A: Features: • Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range&...

floor Price/Ceiling Price

Part Number:
IDT74LVCH32373A
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Features:

• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4 W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in 96-ball LFBGA package
• Balanced Output Drivers: ±24mA
• Reduced system switching noise



Application

• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems



Specifications

Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
0.5 to +6.5
V
TSTG
Storage Temperature
65 to +150
°C
IOUT
DC Output Current
50 to +50
mA
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
50
mA
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.




Description

The IDT74LVCH32373A 32-bit transparent D-type latch is built using advanced dual metal CMOS technology. This high-speed, low-power latch is ideal for temporary storage of data. The device can be used for implementing memory address latches, I/O ports, and bus drivers. The Output Enable and Latch Enable controls are organized to operate each device as four 8- bit latches, two 16-bit latches, or one 32-bit latch. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

All pins of the IDT74LVCH32373A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/ 5V supply system.

The IDT74LVCH32373A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

The IDT74LVCH32373A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.




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