Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = 2.7V to 3.6V, Extended Range• CMOS power levels (0.4 W typ. static)• Rail-to-rail output...
IDT74LVCH2573A: Features: • 0.5 MICRON CMOS Technology• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• VCC = 3.3V ± 0.3V, Normal Range• VCC = ...
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Symbol |
Description |
Max |
Unit |
VTERM |
Terminal Voltage with Respect to GND |
0.5 to +6.5 |
V |
TSTG |
Storage Temperature |
65 to +150 |
°C |
IOUT |
DC Output Current |
50 to +50 |
mA |
IIK IOK |
Continuous Clamp Current, VI < 0 or VO < 0 |
50 |
mA |
ICC ISS |
Continuous Current through each VCC or GND |
±100 |
mA |
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The IDT74LVCH2573A octal transparent D-type latch is built using advanced dual metal CMOS technology. The device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads, and is particularly suitable for implementing buffer registers, input-output (I/ O) ports, bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.
A buffered output-enable (OE) input of the IDT74LVCH2573A can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The IDT74LVCH2573A has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been developed to drive ±12mA at the designated thresholds.
Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V system environment.
The IDT74LVCH2573A has "bus-hold" which retains the inputs' last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.