IDT74LVCH16374A

Features:

* Typical tSK(o) (Output Skew) < 250ps
* ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
   machine model (C = 200pF, R = 0)
*VCC = 3.3V ± 0.3V, Normal Range
*VCC = 2.7V to 3.6V, Extended Range
* CMOS power levels (0.4 W typ. static)
* All inputs, outputs, and I/O are 5V tolerant
* Supports hot insertion
* Available in SSOP, TSSOP, and TVSOP packages


Application

* 5V and 3.3V mixed voltage systems
* Data communication and telecommunication systems


Pinout




Specifications

Symbol	Description	Max	UNITS
VTERM	Terminal Voltage with Respect to GND	0.5 to +6.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	50 to +50	mA
IIK IOK	Continuous Clamp Current, VI < 0 or VO < 0	50	mA
ICC ISS	Continuous Current through each VCC or GND	±100	mA

Description

The IDT74LVCH16374A 16-bit edge-triggered D-type register is built using advanced dual metal CMOS technology. This high-speed, low-power register is ideal for use as a buffer register for data synchronization and storage. The Output Enable (OE) and clock (CLK) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

All pins of the IDT74LVCH16374A can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V/5V supply system.