IDT74LVC823A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The LVC823A 9-bit bus-interface flip-flop is built using advanced dual metal CMOS technology. The LVC823A device is designed specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops of IDT74LVC823A enter data on the low-to-high transitions of the clock. Taking CLKENhigh disables the clock buffer, latching the outputs. This device has noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low, independently of the clock.
A buffered output-enable (OE) IDT74LVC823A input can be used to place the nine outputs in either a normal logic state (high or low logic levels) or a high-impedance state. OEdoes not affect internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.

The LVC823A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor IDT74LVC823A is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of IDT74LVC823A as a translator in a mixed 3.3V/5V system environment.