IDT74LVC821A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

etal CMOS technology. The LVC821A device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

The ten flip-flops IDT74LVC821A are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs.

A buffered output-enable (OE) IDT74LVC821A input can be used to place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state of IDT74LVC821A and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the highimpedance state.

The LVC821A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.

To ensure the high-impedance state during power up or power down, OE IDT74LVC821A should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows he use of IDT74LVC821A as a translator in a mixed 3.3V/5V system environment.