IDT74LVC646A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The LVC646A device consists of bus-transceiver circuits, D-type flipflops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver mode, data present at the highimpedance port is stored in either register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR determines which bus receives data of IDT74LVC646A when OE is low. In the isolation mode (OE high), A data of IDT74LVC646A is stored in one register and B data can be stored in the other register. When an output function is disabled, the input function is still enabled and can be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time. The LVC646A has been designed with a ±24mA output driver. IDT74LVC646A is capable of driving a moderate to heavy load while maintaining  speed performance.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of IDT74LVC646A as a translator in a mixed 3.3V/5V system environment.