IDT74LVC543A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The IDT74LVC543A octal registered transceiver is built using advanced dual etal CMOS technology. The device contains two sets of D-type latches for emporary storage of data flowing in either direction. Separate latch-enable LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided or each register to permit independent control in either direction of data flow.

he A-to-B enable (CEAB) input of the IDT74LVC543A must be low to enter data from A or to utput data to B. If CEAB is low and LEAB is low, the A-to-B latches are ransparent; a subsequent low-to-high transition of LEAB places the A atches in the storage mode. With CEAB and OEAB both low, the 3-state B utputs are active and reflect the data present at the output of the A latches. ata flow for B to A is similar to that of A to B, but uses CEBA, LEBA, and EBA.

The IDT74LVC543A has been designed with a ±24mA output driver. This river is capable of driving a moderate to heavy load while maintaining peed performance. nputs can be driven from either 3.3V or 5V devices. This feature allows he use of this device as a translator in a mixed 3.3V/5V system environment.