IDT74LVC163A

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The LVC163A is a synchronous presettable binary counter, which features an internal look-ahead carry and can be used for high-speed counting. Synchronous operation is provided by having all the flip-flops  clocked simultaniously on the positive-going edge of the clock (CP).

Outputs (Q0 to Q3) IDT74LVC163A may be preset to a high or low level. A low level at the parallel enable input (PE) disables the counting action and causes the data at the data inputs (D0 to D3) to be loaded into the counter on the positive-going edge of the clock (provided that the set-up and hold time requirements for PE are met). Preset of IDT74LVC163A  takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR) sets all four outputs of the flip-flops (Q0 to Q3) to low level after the next positivegoing transition on the clock (CP) input (provided that the set-up and hold time requirements for PE are met).

This action occurs regardless of the levels of CP, PE, CET, and CEP inputs. This synchronous reset feature of IDT74LVC163A enables the designer to modify the maximum count with only one external NAND gate.

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be high to count. The CET input of IDT74LVC163A is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a high output pulse of a duration approximately equal to a high level output of Q0. This pulse of IDT74LVC163A can be used to enable the next cascaded stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula: