IDT74LVC138A

• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

The LVC138A 3-line to 8-line decoder/demultiplexer is built using advanced dual metal CMOS technology. IDT74LVC138A is designed for highperformance memory-decoding or data-routing applications requiring very short propagation delay times. In high performance memory systems, this decoder of IDT74LVC138A minimizes the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions of IDT74LVC138A at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low enable inputs and one activehigh enable input reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of IDT74LVC138A as a translator in a mixed 3.3V/5V supply system.

The LVC138A has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.