IDT74GTLP306

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Unused inputs without Bus-Hold must be held HIGH or LOW.

The GTLP306 is an 8-bit bus transceiver. IDT74GTLP306 provides signal level translation, from LVTTL to GTLP, for applications requiring a high-speed interface between cards operating at LVTTL logic levels and back-planes operating at GTLP logic levels. GTLP IDT74GTLP306 provides reduced output swing (<1V), reduced input threshold levels, and output edge-rate control to minimize signal setting times. The GTLP306 is a derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates internal edge-rate control, which is process, voltage, and temperature (PVT) compensated.

The GTLP306 combines a transceiver function with an LVTTL to GTLP translation. Data polarity is non-inverting, and the data flow direction is controlled by the T/R pin. The outputs are enabled to allow data through the device when OE is low. Otherwise, both A and B are placed in a highimpedance state.

GTLP output low voltage is less than 0.5V. The output of IDT74GTLP306 high is 1.5V, and the receiver threshold is 1V.