Features: • Bus switches provide zero delay paths• Extended commercial range of 40°C to +85°C• Low switch on-resistance: FST163xxx 4Ω• TTL-compatible input and output levels• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF,...
IDT74FST163232: Features: • Bus switches provide zero delay paths• Extended commercial range of 40°C to +85°C• Low switch on-resistance: FST163xxx 4Ω• TTL-compatible input and output ...
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Symbol | Description | Max. | Unit |
VTERM(2) | Terminal Voltage with Respect to GND | 0.5 to +7.0 | V |
TSTG | Storage Temperature | 65 to +150 | |
IOUT | Maximum Continuous Channel Current | 128 | mA |
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condiitions for extended periods may affect reliability.
2. VCC, Control and Switch terminals.
The IDT74FST163232 belong to IDT's family of Bus switches.Bus switch devices perform the function of connecting or solating two ports without providing any inherent current sink or source capability. Thus they generate little or no noise of heir own while providing a low resistance path for an external driver. These devices connect input and output ports through an n-channel FET. When the gate-to-source junction of this FET is adequately forward-biased the device conducts and the resistance between input and output ports is small. Without adequate bias on the gate to-source junction of the FET, the FET is turned off, therefore with no VCC applied, the device has hot insertion capability.
The low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero.
The IDT74FST163232 provides three 16-bit TTL- compatible ports that support 2:1 multiplexing. The S0,1 pins control mux select and switch enable/disable. The S0,1 inputs are synchronous and clocked on the rising edge of CLK when CLKEN is low.