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IDT74FCT810BT

Features: • 0.5 MICRON CMOS Technology• Guaranteed low skew < 600ps (max.)• Very low duty cycle distortion < 700ps (max.)• Low CMOS levels• TTL compatible inputs and outputs• TTL level output voltage swings• High drive: -32mA IOH, +48mA IOL• Tw...

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SeekIC No. : 004373079 Detail

IDT74FCT810BT: Features: • 0.5 MICRON CMOS Technology• Guaranteed low skew < 600ps (max.)• Very low duty cycle distortion < 700ps (max.)• Low CMOS levels• TTL compatible inputs ...

IDT74FCT810BT Data Sheet

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Part Number:
IDT74FCT810BT
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 600ps (max.)
• Very low duty cycle distortion < 700ps (max.)
• Low CMOS levels
• TTL compatible inputs and outputs
• TTL level output voltage swings
• High drive: -32mA IOH, +48mA IOL
• Two independent output banks with 3-state control:
One 1:5 inverting bank
One 1:5 non-inverting bank
• Available in QSOP, SSOP, and SOIC packages


Pinout

Connection Diagram


Specifications

Symbol
Description
Max
Unit
VTER(2)
Terminal Voltage with Respect to GND
0.5 to +7
v
TSTG
Storage Temperature
65 to +165
°C
IOUT
Junction Temperature
60 to +60
mA

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.


Description

The IDT74FCT810BT is a dual bank inverting/ non-inverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The FCT810T has low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs of the IDT74FCT810BT are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance.




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