IDT74FCT299

Features:

• IDT54/74FCT299 equivalent to FAST speed
• IDT54/74FCT299A 25% faster than FAST
• IDT54/74FCT299C 35% faster than FAST
• Equivalent to FAST output drive over full temperature and voltage supply extremes
•IOL = 48mA (commercial) and 32mA (military)
• CMOS power levels (1mW typ. static)
• TTL input and output level compatible
• CMOS output level compatible
• Substantially lower input current levels than FAST (5µA max.)
• 8-input universal shift register
• JEDEC standard pinout for DIP and LCC
• Product available in Radiation Tolerant and Radiation Enhanced versions
• Military product compliant to MIL-STD-883, Class B
• Standard Military Drawing# 5962-86862 is listed on this function.  Refer to section 2.


Pinout




Specifications

Symbol            Rating                                                      Commercial             Military                       Unit
VTERM(²)        Terminal with Respect to GND Voltage     0.5 to +7.0           0.5 to +7.0              V

VTERM(3)        Terminal with Respect to GND Voltage     0.5 to VCC            0.5 to VCC               V

TA                   Operating Temperature                            0 to +70                  55 to +125              °C

TBIAS              Temperature Under Bias                          55 to +125            65 to +135              °C

TSTG               Storage Temperature                               55 to +125            65 to +150              °C

PT                   Power Dissipation                                     0.5                            0.5                             W

IOUT               DC Output Current                                    120                           120                            mA


Description

The IDT74FCT299 are built using an advanced dual metal CMOS technology.  The IDT54/74FCT299 and IDT54/74FCT299A/C are 8-input universal shift/storage registers with 3-state outputs.  Four modes of operation are possible: hold (store), shift left, shift right and load data.  The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins.  Additional outputs are provided for flip-flops Q0 and Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.