IDT74FCT2573AT

Features: • A and C grades• Low input and output leakage 1A (max.)• CMOS power levels• True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)• Resistor outputs (-15mA IOH, 12mA IOL)• Meets or exceeds JEDEC standard 18 specifications•...

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IDT74FCT2573AT Picture
SeekIC No. : 004373009 Detail

IDT74FCT2573AT: Features: • A and C grades• Low input and output leakage 1A (max.)• CMOS power levels• True TTL input and output compatibility: VOH = 3.3V (typ.) VOL = 0.3V (typ.)• R...

floor Price/Ceiling Price

Part Number:
IDT74FCT2573AT
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/22

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Product Details

Description



Features:

• A and C grades
• Low input and output leakage 1A (max.)
• CMOS power levels
• True TTL input and output compatibility:
  VOH = 3.3V (typ.)
  VOL = 0.3V (typ.)
• Resistor outputs (-15mA IOH, 12mA IOL)
• Meets or exceeds JEDEC standard 18 specifications
• Reduced system switching noise
• Available in SOIC, QSOP, and TSSOP packages



Pinout

  Connection Diagram


Specifications

Symbol

Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
0.5 to VCC+0.5
V
TSTG
Storage Temperature
65 to +150
°C

IOUT

DC Output Current
60 to +120
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.




Description

The IDT74FCT2573AT is an octal transparent latch built using advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OEis high, the bus output is in the high-impedance state.

The IDT74FCT2573AT has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The FCT2573T parts are plug-in replacements for FCT573T parts.




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