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IDT74FCT16823CT

Features: • 0.5 MICRON CMOS Technology• High-speed, low-power CMOS replacement for ABT functions• Typical tSK(o) (Output Skew) < 250ps• Low input and output leakage 1A (max.)• VCC = 5V ± 10%• High drive outputs (-32mA IOH, 64mA IOL)• Power off disable o...

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SeekIC No. : 004372969 Detail

IDT74FCT16823CT: Features: • 0.5 MICRON CMOS Technology• High-speed, low-power CMOS replacement for ABT functions• Typical tSK(o) (Output Skew) < 250ps• Low input and output leakage 1A (ma...

IDT74FCT16823CT Data Sheet

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Part Number:
IDT74FCT16823CT
Supply Ability:
5000

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  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 0.5 MICRON CMOS Technology
• High-speed, low-power CMOS replacement for ABT functions
• Typical tSK(o) (Output Skew) < 250ps
• Low input and output leakage 1A (max.)
• VCC = 5V ± 10%
• High drive outputs (-32mA IOH, 64mA IOL)
• Power off disable outputs permit "live insertion"
• Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C
• Available in SSOP and TSSOP packages


Pinout

Connection Diagram


Specifications

Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
VTERM(3)
Terminal Voltage with Respect to GND
0.5 to VCC+0.5
V
TSTG
Storage Temperature
65 to +150
°C

IOUT
DC Output Current
60 to +120
mA

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.




Description

The IDT74FCT16823CT 18-bit bus interface registers are built using advanced, dual metal CMOS technology. These high-speed, low-power registers with clock enable (xCLKEN) and clear (xCLR) controls are ideal for parity bus interfacing in high-performance synchronous systems. The control inputs are organized to operate the device as two 9-bit registers or one 18-bit register. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.

The IDT74FCT16823CT is ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.




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