Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP• Extended ...
IDT74FCT163601A: Features: • 0.5 MICRON CMOS Technology• Typical tSK(o) (Output Skew) < 250ps• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)•...
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Symbol | Description | Max. | Unit |
VTERM(2) |
Terminal Voltage with Respect to GND | 0.5 to +4.6 | V |
VTERM(3) |
Terminal Voltage with Respect to GND |
0.5 to +7.0 | V |
VTERM(4) |
Terminal Voltage with Respect to GND |
0.5 to VCC + 0.5 |
V |
TSTG | Storage Temperature | 65 to +150 | °C |
IOUT | DC Output Current | 60 to +60 | mA |
The IDT74FCT163601A 18-bit registered transceiver is built using advanced dual metal CMOS technology. These 18-bit universal bus transceivers combine D-type latches and Dtype flip-flops to allow data flow in transparent, latched and clocked modes.
Data flow in each direction of the IDT74FCT163601A is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock(CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB is active low.When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.Data flow for B to A is similar to that of A to B but uses OEBA,LEBA, CLKBA and CLKENBA.The IDT74FCT163601A has series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.