IDT74FCT163543

•0.5 MICRON CMOS Technology
•Typical tSK(o) (Output Skew) < 250ps
•ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
•Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP
•Extended commercial range of -40to +85
•VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range
•CMOS power levels (0.4mW typ. static)
•Rail-to-Rail output swing for increased noise margin
•Low Ground Bounce (0.3V typ.)
•Inputs (except I/O) can be driven by 3.3V or 5V components

The FCT163543/A/C 16-bit latched transceivers are built using advanced dual metal CMOS technology. These highspeed, low-power devices of IDT74FCT163543 are organized as two independent 8- bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be LOW in order to enter data from the A port or to output data from the B port. xLEAB controls the latch function. When xLEAB is LOW, the latches are transparent. A subsequent LOW-to- HIGH transition of xLEAB signal puts the A latches in the storage mode. XOEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using xCEBA , xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs of IDT74FCT163543 are designed with hysteresis for improved noise margin.

The FCT163543/A/C have series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall timesreducing the need for external series terminating resistors.