IDT74FCT163501A

Features:

• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
         > 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4mW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V components


Pinout




Specifications

ABSOLUTE MAXIMUM RATINGS(1)

Symbol	Description	Max.	Unit
VTERM(2)	Terminal Voltage with Respect to GND	0.5 to +4.6	V
VTERM(3)	Terminal Voltage with Respect to GND	0.5 to +7.0	V
VTERM(4)	Terminal Voltage with Respect to GND	0.5 to VCC + 0.5	V
TSTG	Storage Temperature	65 to +150	°C
IOUT	DC Output Current	60 to +60	mA

                                                                                                 2776 lnk 03
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Vcc terminals.
3. Input terminals.
4. Output and I/O terminals.


Description

The FCT163501/A/C 18-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit registered bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, IDT74FCT163501A operates in transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level.If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. EAB performs the output enable function on the B port. Data flow from B port to A port is similiar but requires using OEBA, LEBA and CLKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.The FCT163501/A/C have series current limiting resistors. IDT74FCT163501A offer low ground bounce, minimal undershoot, and controlled output fall times-reducing the need for external series terminating resistors.