IDT74AUC164245

NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

This 16-bit level shifting bus transceiver is built using advanced CMOS technology. The AUC164245 is ideal for asynchronous communications between data buses. The control function implementation minimizes external timing requirements.

The AUC164245 16-bit level shifting bus transceiver contains two separate supply rails. The B port is designed to track VDDB, which accepts voltages from 0.8V to 2.7V. The A port and control inputs are designed to track VDDA, which accepts voltages from 0.8V to 2.7V. IDT74AUC164245 allows for user-selectable translation for various level shifting system environments.

IDT74AUC164245 can be used as one 16-bit transceiver or two 8-bit transceivers. IDT74AUC164245 allows data transmission from A bus to B bus or from B bus to A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

IDT74AUC164245 is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The AUC164245 A and B ports are designed with ±9mA output drivers.

IDT74AUC164245 are capable of driving moderate loads while maintaining high speed performance. To ensure the high-impedance state during power up or power down, OE should be tied to VDDA through a pull-up resistor; the minimum value of the resistor is IDT74AUC164245 determined by the current-sinking capability of the driver.