IDT74AUC16374

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.


Description

This 16-bit edge-triggered D-type flip-flop IDT74AUC16374 is built using advanced CMOS technology.

The AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs. OE IDT74AUC16374 can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state of IDT74AUC16374 and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not affect the internal operation of the flip-flop.

Old data can be retained or new data can be entered while the outputs are in the high-impedance state. IDT74AUC16374 is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the outputs, preventing damaging current backflow through IDT74AUC16374 when it is powered down.

To ensure the high-impedance state during power up or power down, OE IDT74AUC16374 should be tied to VDD through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.