IDT74AUC16373

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

This 16-bit transparent D-type latch is built using advanced CMOS technology. IDT74AUC16373 can be used as a single 16-bit latch or as two 8-bit latches. When the latch enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output enable (OE)IDT74AUC16373 input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The OE input does not affect the internal operation of the latch. IDT74AUC16373 is fully specified for partial power-down applications using IOFF.

The IOFF circuitry disables the outputs, preventing damaging current backflow through IDT74AUC16373 when it is powered down. To ensure the high-impedance state during power up or power down, OE IDT74AUC16373 should be tied to VDD through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.