IDT74ALVCH32245

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V_CC terminals. 3. All terminals except V_CC.

This 32-bit bus transceiver IDT74ALVCH32245 is built using advanced dual metal CMOS technology. This high-speed IDT74ALVCH32245, low power transceiver is ideal for asynchronous communication between two busses (A and B). The Direction and Output Enable controls are designed to operate the device as either four independent 8-bit transceivers or one 32-bit transceiver. The direction control pins (DIR) of IDT74ALVCH32245 control the direction of data flow. The output enable pins (OE) override the direction control and disable both ports. All inputs are designed with hysteresis for improved noise margin.

The ALVCH32245 has been designed with a ±24mA output driver. IDT74ALVCH32245 is capable of driving a moderate to heavy load while maintaining speed performance.

The ALVCH32245 has "bus-hold" which retains the inputs' last state whenever the input bus goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.